The present invention relates, in general, to the field of integrated circuit (xe2x80x9cICxe2x80x9d) memory devices and those ICs incorporating embedded dynamic random access memory (xe2x80x9cDRAMxe2x80x9d). More particularly, the present invention relates to a data path decoding technique of especial applicability to DRAM devices and those ICs incorporating an embedded memory array.
In typical embedded DRAM architectures, local and global data read/write lines are often employed. In operation, the local read/write lines need to be selectively connected and disconnected to the global read/write lines as various sub-arrays are selected and de-selected to preclude data bus contention. In most designs, the local data lines tend to become relatively long with concomitantly large resistance and capacitance then resulting. Moreover, if the page length becomes long, a great deal of on-chip area is consumed with the routing of column address lines. For example, with sixteen bit column designs, column lines Y0 through Y15 must generally be routed through the sense amplifier region itself.
The data path decoding technique and architecture of the present invention advantageously obviates the shortcomings of these prior designs by providing what is, in essence, a second level of decoding. This uniquely results in a need for fewer column select lines and even shorter local data lines. Further, the technique and architecture of the present invention requires no additional on-chip area to that of prior techniques and adds no new gate delays or pass gates to the critical read data or write data paths. This is accomplished by effectively incorporating an address function in with the read/write enable (xe2x80x9cRWENxe2x80x9d) or separate read enable (xe2x80x9cRENxe2x80x9d) and write enable (xe2x80x9cWENxe2x80x9d) signals. Consequently, half as many column select lines need be routed to the sense amplifiers since a second level of column decoding is thereby provided.
Particularly disclosed herein is an integrated circuit device including a memory array having a data path which comprises N column lines and first and second groups of N sense amplifiers respectively couplable to first and second pairs of complementary local data lines in response to signals on the N column lines. First and second local read/write circuits are respectively coupled to the first and second pairs of complementary local data lines and complementary global data lines are selectively couplable to either of the first and second pairs of complementary local data lines in response to first and second enable signals applied to the first and second local read/write circuits.
Further disclosed herein is an integrated circuit device including a memory array having a data path which comprises N read column lines and N write column lines. First and second groups of N sense amplifiers are respectively couplable to first and second pairs of complementary local data read lines in response to signals on the N read column lines and to first and second pairs of complementary local data write lines in response to signals on the N write column lines. First and second local read circuits are respectively coupled to the first and second pairs of complementary local data read lines and first and second local write circuits are also respectively coupled to the first and second pairs of complementary local data write lines. Complementary global data read lines are selectively couplable to either of the first and second pairs of complementary local data read lines in response to first and second read enable signals applied to the first and second local read circuits and complementary global data write lines are selectively couplable to either of the first and second pairs of complementary local data write lines in response to first and second write enable signals applied to the first and second local write circuits.